1. Field of the Invention
The present invention relates to signal integrators, and in particular, to signal integrators for integrating continuous and discrete signals.
2. Prior Art
Achieving linear integration of two different types of inputs, such as a continuous current and a discrete charge, is complicated by the slewing of the integrated signal caused by the effects of integrating discrete charges along with the continuous current. Compensating for these nonlinear effects, e.g., through the use of filters when possible, increase the size and complexity of the system, as well as power consumption, any and all of which are problematic for many applications, particularly in mobile devices or instrumentation systems.
Referring to FIG. 1A, a conventional circuit for integrating continuous current and discrete charge receives a continuous output current I resulting from the application of an input voltage VIN to an input resistance R1. The discrete charge Q is received from an input capacitance C1 which is alternately charged and discharged by the application of reference voltages VREF1, VREF2 and a common mode voltage VCM (discussed in more detail below). This current I and charge Q are summed at a virtual ground VG formed at the inverting input electrode of an operational amplifier A1 whose non-inverting input electrode is grounded. Due to the feedback capacitance Cf connected between the inverting input electrode and output electrode of the operational amplifier A1 (in accordance with well known integrator principles), the summed current I and charge Q is accumulated on the feedback capacitance Cf forced by the virtual ground VG at the inverting input electrode of the operational amplifier A1.
The input capacitance C1 is alternately charged and discharged by the alternate application of the reference voltages VREF1, VREF2 and common mode voltage VCM during alternate time intervals, e.g., mutually exclusive, in accordance with switch control signals F1, F2 having mutually opposing signal assertion and de-assertion phases.
Referring to FIG. 1B, the input capacitance C1 is disconnected from the virtual ground at the inverting input electrode of the operational amplifier A1 during assertion of signal F2 (reset phase), and its electrodes, or plates, are set to a reference voltage VREF1 and the common mode voltage VCM. During assertion of signal F1 (integrating phase), the top electrode of the input capacitance C1 is connected to the virtual ground at the inverting input electrode of the operational amplifier A1, while the bottom electrode of the input capacitance C1 is connected to the reference voltage VREF2. The resulting voltage difference VREF1-VREF2 across the input capacitance C1 produces the charge Q, which is transferred and accumulated on the feedback capacitance Cf. Because the voltage across the input capacitance cannot be changed instantly, there will be a voltage transient at the bottom electrode of the input capacitance C1, as well as at the top electrode and virtual ground VG. As is well known, the transconductance Gm of the operational amplifier A1 is dependent upon its input voltage, i.e., voltage applied between its inverting and non-inverting electrodes. Accordingly, any voltage transient appearing across these input electrodes alters the transconductance Gm and, therefore, disturbs linear operation of the operational amplifier, in which, in this application, results in a disturbance in linear integration of the continuous input current I. As the voltage transient at the virtual ground VG increases, distortions in the integrated signal increase as well.